Senior Hardware Verification Engineer at Mentor Graphics
Location: Nasr City
• B.Sc. Electronics or Computer with V. Good with honor (minimum).
• Solid experience with UVM verification methodology and Verilog HDL (2+ years).
• Knowledge of FPGA Design Flow and Digital HW Verification
• A very good communicator in English, proactive, and team player.
• Performing activities including: Reading JEDEC standards of memory Protocols, testing them using UVM methodology & simulation & emulation based verification and debug.
• Taking responsibility for product-level model verification.
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- Seniority Junior (1 to 3 years)
- Employer type Multinational Company
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March 1 - March 2
March 8 @ 5:00 pm - March 12 @ 9:00 pm EET
March 29 @ 4:00 pm - May 3 @ 9:00 pm EET
April 22 @ 1:00 pm - November 30 @ 5:00 pm EET